EXPERTISE
     

HIGH-PERFORMANCE ANALOG AND MIXED-SIGNAL

  • Bandgap references: low-voltage (LV) and high-voltage (HV)
  • Instrumentation amplifiers: chopping amplifiers
  • Low drop out (LDO) regulators
  • Low-noise switched capacitor circuits
  • Low-noise correlated double sampling (CDS) sample & holds
  • Operational transconductance amplifiers (OTAs): offset compensation
  • Phase-locked loops (PLL): low jitter, delta-sigma fractional-N synthesis
  • Reference buffers
  • High-precision, temperature-stable Xtal-less oscillators
  • Digital-to-analog (DA) converters: high-accuracy, high-yield, fast-settling
  • Delta-Sigma (ΔΣ) analog-to-digital (AD) converters: continuous and discrete time
  • Successive approximation AD converters
  • Pipeline AD converters
  • Inductive bi-directional low-datarate link
  • Monolithic oscillators with low-phase noise
  • Ultralow-power circuits

QUALITY ASSURANCE

  • High-quality foundry selection: We only work with the best foundries to guarantee that the ASICs you get are of the highest quality.
  • Design and validation reporting: We are known for our open communication and close involvement. We document every phase of the design, and we commit to high-quality reports. Through bi-weekly reports, calls and regular on-site meetings, we closely involve our customers in the design process.
  • Package selection : We select the most optimal package for your application, together with our partners that are longstanding experts in the field.
  • Bench testing: In our in-house lab, our engineers analyse your ASICs on custom-designed test boards.
  • ATE production tests and calibration: Every chip is verified using a custom-developed ATE (automated test equipment) test program. Only known good dies are shipped.. As part of the ATE procedure, the chips can be calibrated and custom programmed according to your needs.
  • Statistical tests (CPK) and industrialisation/skew lots:  We do our statistical analysis on a large number of ATE-tested samples to guarantee high yields and low ASIC unit prices. During skew lots, process variations are deliberately introduced to stretch the ASICs to their boundaries. This is to guarantee the robustness of the ASICs over process corners and potential drifts.
  • ESD and latch-up tests: These tests are performed to ensure a high reliability of the ASIC.
  • ISO 9001:2008 procedures: The internal project flow is subject to the ISO procedures, ensuring our deliverables meet the highest quality.
  • Project management: Integrated Circuit Designs assigns a single point of contact to your project and manages the complete cycle. From initial study to the ASIC in mass production.

DEVELOPMENT AND SUPPLY SERVICES
This is how we can help in the 3 phases of a typical ASIC development:

PHASE 1: SPECIFICATION AND ARCHITECTURAL DESIGN

The purpose of this phase is to gather all information to allow you to evaluate your business case. This basically consists of:
  • the ASIC specification
  • the ASIC unit cost
  • a project plan and budget

The ASIC specification is the sign-off reference for the project. In this document, our engineers summarize the results of their in-depth study, which includes: a feasibility assessment, optimal architecture with specifications, the rationale for these specifications, preferred technology, external components, assembly, test strategies (DFT=Design For Test), and risk mitigations. Our project team conceives the architecture and requirements in close cooperation and interaction with your technical team. They immerse themselves in all aspects of your system to arrive at a low risk, high-performance, and cost-optimized ASIC solution. The architecture is always proven by extensive mixed-signal system modeling and simulations.
ASIC specification and architectural design allows us to set up a detailed project plan, including NRE costs for design, prototyping, and production. We fix the total project cost at the end of this phase to minimize your financial risk.
ASIC unit cost is based on our area estimate, your product volume targets, the preferred package, and the estimated production test time.
This information allows you to make your decision on whether to continue to ASIC development with Integrated Circuit Designs.

PHASE 2: ASIC DEVELOPMENT

In this phase, we execute the plan and architecture of Phase 1: the mixed-signal design and layout of the ASIC. Our engineers perform elaborate simulations of process, voltage, and temperature (PVT) variations, and statistical mismatch for specification compliance under all conditions. We take into account all (parasitic) effects of the physical implementation, and of the system within it is embedded. 
After thorough verification and review, we begin the prototype fabrication: the tape-out. We choose the most cost-effective fabrication method that yields sufficient samples for statistical analysis. In parallel, we coordinate the development of the production test (ATE=Automated Test Equipment) hardware and software, and develop prototype test boards in accordance with the test strategy (DFT). In addition, we provide all necessary information to embed the ASIC in your application.
When the silicon returns from the fab, we perform prototype tests in our measurement lab. The production tests are run in parallel to obtain statistical data. Full characterization of the ASICs’ over temperatures and supply voltages is done on the ATE tools to ensure a high yield and low ASIC cost. Finally, the ASIC is subjected to ESD (electrostatic discharge) and latch-up tests to ensure high reliability of the ASIC in the field. We cross-check the results of all tests and your field tests for full correlation.
You receive samples as soon as the first functional tests are completed. The functional ASIC prototypes can already be integrated in your application for demonstration purposes, field tests, pre-production series, and so forth.  We provide support in the integration and testing of your application. After all tests have been completed, we continue to fine-tune the ASIC for optimal performance and cost-effectiveness, and resolve any outstanding issues in the prototypes. In addition, we offer the possibility to add new features or improvements to the ASIC based on your field tests. 
After a short design and layout iteration, optimized ASIC prototypes are fabricated and the tests repeated to ensure full compliance with the specification. We also optimize the ATE program to further reduce production test time, and thus ASIC unit price. The ASIC is now fully compliant and cost optimized, ready for qualification and production.

PHASE 3: QUALIFICATION AND PRODUCTION

The purpose of this phase is to deliver well-established ASICs in your target volumes. 
A Single Layer Maskset (SLM) is generated to start volume production. The ASIC is first qualified by means of an industrialization lot (of a few batches) and, depending on your volume, a skew lot. From the devices in the industrialization lot, we collect statistical data and freeze the production test limits. The skew lot is processed to prove the robustness of the ASIC over process variations, and to guarantee the final yield. 
Extra qualification tests can be carried out depending on the specific environmental operating conditions of the ASIC (“the mission profile”), and/or specific customer requests to ensure long-term ASIC compliance in the field. 
Every ASIC we provide is tested for compliance with the ASIC production-test specification, ensuring product success. 
 

MEMS SENSOR-ACTUATOR INTERFACING

 

  • Resistive sensor interfaces: Wheatstone bridge readout
  • Capacitive sensor interfaces: tilt, accelerometer, pressure sensors, …
  • Magnetic sensor interfaces: Hall sensors, GMR (giant magneto resistance) sensor interface
  • Inductive proximity sensor architectures
  • High accuracy, fully integrated temperature sensors
  • Delta-Sigma (ΔΣ) analog-to-digital (AD) converters: continuous and discrete time
  • Successive approximation AD converters

POWER MANAGEMENT

 

  • LDO regulators: low quiescent current / high current output
  • Protection circuits: current, voltage and temperature overprotection
  • Integrated switching-mode power supplies (highly-efficient DC-DC converters):
  • Buck, boost, buck/boost, fly-back
  • Continuous and discontinuous
  • Voltage and current mode
  • Single phase or multiphase
  • High-frequency - small inductance
  • Asynchronous and synchronous
  • Pulse width modulation (PWM) – Pulse frequency modulation (PFM)
  • Integrated charge pumps and voltage doublers
  • Wireless charging and battery management: state-of-charge, state-of-health.

HIGH-VOLTAGE IC DESIGN

 

  • High-voltage (bi-directional) switches
  • High-voltage I/O buffers
  • Class AB/G/H amplifiers
  • Class D audio amplifiers
  • (Self-oscillating) power amplifiers
  • High-voltage low drop out (LDO) regulators and bandgap references
  • High-voltage DC-DC converters: capacitive and inductive, buck, boost, buck-boost, flyback, converters and controllers
  • High-voltage charge pumps and voltage doublers
  • High-voltage instrumentation front-ends
  • H-bridge (e.g. motor steering applications)
  • MEMS and piezo drivers (ultrasound)
  • High-voltage drivers:

      - MEMS drivers
      - Line drivers
      - Gate drivers
      - Laser/LED/LCD/backlight drivers
      - Low-side (LS) and high-side (HS) drivers
      - Electrode-array drivers (brain, nerve interfaces)
      - Solenoid (coil) driver

DESIGN ENVIRONMENT
Integrated Circuit Designs has developed a unique design environment for high-quality analog and digital design in a structured way, resulting in a high reliability and high first-time-right success rate.

INDUSTRY-STANDARD EDA TOOLS

  • State-of-the-art simulators for analog, digital and mixed-signal ICs (see above). Integrated Circuit Designs has developed methodologies to have fast and accurate full chip-level mixed-signal simulation coverage with these simulators.
  • Cadence - Virtuoso for schematic entry and layout 
  • Industry-standard digital tool flow enhanced with in-house tools: simulation, synthesis, logic equivalence checking, STA, formal verification, place-and-route and ATPG test pattern generation
  • Mentor Calibre for physical Verification (DRC/LVS) and parasitic extraction (xRC) 
  • Cliosoft for version control of the schematics, layout and testbench files
  • Matlab (including custom toolboxes) and Simulink for concept definitions and system design
  • Matlab script-based interface to formalize and automate circuit sizing, test-bench and simulation control, simulation data post-processing and report generation

STRUCTURED DESIGN METHODOLOGY

  •  Key benefits:
    • Structured and formalized design approach using design plans
    • Traceability of design choices and trade-offs through version control and design plans
    • Design and layout integrity through version control (Cliosoft)
    • Quality of final design and layout by formal issue management (JIRA)
    • Reliability of results by semi-automated simulation coverage and reporting
    • Extensive digital simulation coverage and constraint randomized verification

 Key Features:

    • Top-down, bottom-up design methodology
    • Automated characterization over corners, supply and temperature
    • Powerful simulation result and corner data processing
    • Technology-independent platform
    • Simulator-independent platform
    • Embeds design plans for most analog blocks e.g. amplifier topologies, low dropout regulators, oscillators, bandgap references, temperature sensors, ...
    • Code, condition, functional and assertion coverage in digital simulation
    • Version control (Cliosoft)
    • Issue management (JIRA)

PROPRIETARY DESIGN TOOLBOXES

    • DC-DC converters (inductive and capacitive / buck, boost, buck-boost, flyback)
    • Delta-sigma analog-to-digital converters
    • SAR analog-to-digital converters
    • Pipelined analog-to-digital converters
    • Delta-Sigma fractional-N synthesizers
    • Digital-to-analog converters
    • Phase-locked loops (PLL)

 

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